Chiplet Architecture is the Future

The shift from monolithic system-on-chip (SoC) designs to chiplet-based architectures is not simply architectural; it raises the bar for advanced packaging, where hybrid bonding has emerged as a cornerstone technology.

Presenting Hardware-Level Security for Detecting Counterfeits (media alert)

Woychik and Asadi’s team from U. of Florida will detail a hardware-level security framework for detecting counterfeit parts and materials.

Presenting Hybrid Bonding Reliability at 2026 ECTC in Orlando (media alert)

Woychik and Asadi’s team from U. of Florida will detail a new predictive reliability model for hybrid bonding.

Hybrid Bonding Everywhere

The real challenge with hybrid bonding is maintaining a robust and repeatable production cycle.

Bigger is Better?

Charles Woychik explains why bigger TSVs can be a better solution.

The Unfinished Revolution

Advanced Packaging and Heterogeneous Integration: Amazing breakthroughs lie ahead. It won’t be easy — but it will be awesome.

Hybrid Bonding Symposium 2026

Hybrid Bonding empowers the new chiplet paradigm and Foundry 2.0.

Evolution of Electronics Packaging

Charles Woychik at IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE), October 2025.

Global View vs US Focus on OSATs

Charles Woychik at Counterfeit Parts & Materials symposium, June 2025.

Key Terms

  • 2.5D: An advanced packaging technology that interconnects components on an interposer within a single packaged device.
  • Chiplet: An unpackaged IC that contains a well-defined subset of functionality, designed to be integrated with other components into a finished device.
  • Foundry 2.0: A manufacturing model that takes building blocks from traditional semiconductor manufacturers and uses advanced packaging and additive manufacturing to create highly customized devices.
  • Heterogeneous Integration: The combining of different types of integrated circuitry in a single device; differences may be in process, node, substrate, source, or function.
  • Through Silicon Via (TSV): A vertical electrical connection that pierces the substrate.
  • W2W: Wafer-to-Wafer (also wafer-on-wafer) stacking: bonding and integrating whole processed wafers atop one another before dicing the stack.