**[2.5D](/content/technologies/#2.5D):** An advanced packaging technology that interconnects components on an interposer within a single packaged device.

**[3D](/content/technologies/#3D/index.html):** An advanced packaging technology that incorporates multiple layers of co-designed circuitry into a single chip, integrated both vertically and horizontally.

**[3DIC](/content/technologies/#3D/index.html) (also 3D IC, 3D-IC):** A multi-layer integrated circuit formed using 3D advanced packaging technology.

[**Advanced Packaging**](/content/services/advanced-packaging/index.html): Any of several processes, typically performed at semiconductor fabrication facilities, that aggregate and interconnect multiple components into an assembly that acts as a single electronic device.

**AI:** Artificial Intelligence

**ARC:** Anti-Reflective Coating

**Artificial Intelligence:** see AI.

**BEoL:** Back End of Line: Semiconductor manufacturing processes that occur after a wafer has been patterned with transistors, capacitors, resistors, etc.

**Carrier Wafer:** A wafer that is used to hold components during intermediate steps, but is not a part of the finished device.

**Chip:** An integrated circuit (IC); may be an unpackaged die or a finished device.

**[Chiplet](/content/technologies/chiplets/index.html):** A modular unpackaged IC containing a well-defined subset of functionality, designed to be integrated with other components into a finished device.

**Cleanroom (or clean room):** A space engineered to maintain a very low concentration of airborne particles.

**CMP:** Chemical Mechanical Polishing, also called chemical mechanical planarization.

**CoW:** Chip-on-Wafer; see D2W

**D2D:** Die-to-Die (also die-on-die) stacking: Bonding and integrating individual dies atop one another.

**D2W:** Die-to-Wafer (also die-on-wafer or chip-on-wafer) stacking: Bonding and integrating dies onto a wafer before dicing the wafer.

**[DBI®](/content/technologies/hybrid-bonding/index.html):** Direct Bond Interconnect: A bump-less hybrid bonding technology (developed by Ziptronix) practiced by NHanced.

**DBI Ultra:** A DBI process that bonds dies rather than wafers.

**Dicing:** Cutting a processed semiconductor wafer into separate dies.

**Die:** An unpackaged integrated circuit; a rectangular piece cut (diced) from a processed wafer.

**Die on Die:** See D2D.

**Die on Wafer:** See D2W.

**Direct Bond Interconnect:** see DBI.

**FEoL:** Front End of Line: Processes in semiconductor manufacturing that create patterns of elements (transistors, capacitors, resistors, etc.) on a wafer.

**[Foundry 2.0](/content/foundry-2-0/index.html):** A manufacturing model that takes building blocks from traditional semiconductor manufacturers and uses advanced packaging and additive manufacturing to create highly customized devices.

**HAST:** Highly Accelerated Stress Test

**HDI:** High Density Interconnect

**Hermetic Seal:** A tight seal that prevents penetration of moisture and gases.

**[Heterogeneous Integration](/content/technologies/heterogeneous-integration/index.html):** see HI

**[HI](/content/technologies/heterogeneous-integration/index.html):** Heterogeneous Integration: the combining of different types of integrated circuitry in a single device; differences may be in process, node, substrate, source, or function.

**HNA:** Hydrofluoric / Nitric / Acetic acids: An extremely aggressive mixture used as a wet etchant.

**[Hybrid Bonding](/content/technologies/hybrid-bonding/index.html):** An oxide-to-oxide dielectric bond plus an embedded metal-to-metal bond.

**IC:** Integrated Circuit: An electronic circuit formed directly on semiconductor material.

**Integrated Circuit:** See IC.

**Interconnect:** Wires or traces that carry signals between the elements in an electronic device.

**[Interposer](/content/technologies/interposers/index.html):** A piece of semiconductor material (glass, silicon, silica, or organic) built to host and interconnect two or more components in a single 2.5D package.

**IoT:** Internet of Things: The interconnection (via the Internet) of small devices embedded in everyday objects.

**[Micro-Transfer Printing](/content/2020/11/17/micro-transfer-printing/index.html)(MTP):** A technology developed by X-Celeprint that uses a flexible stamp to transfer very small, thin chiplets from a source wafer to a target wafer for 3D stacking.

**Moore’s Law:** An observation by Gordon Moore that the number of transistors per square inch on ICs doubled every two years, and the prediction that they would continue to do so.

**More than Moore:** A catch-all phrase for technologies that attempt to extend Moore’s Law by creating smaller, faster, or more powerful circuitry without shrinking the size of the transistor.

**MRAM:** Magnetoresistive Random-Access Memory: A robust non-volatile memory that stores data in magnetic domains.

**MTP:** See Micro Transfer Printing.

**Non-Recurring Engineering:** One-time costs to research, design, develop, and test a new product.

**Node:** See Process Node.

**NRE:** See Non-Recurring Engineering.

**Oxide Bonding:** A process that forms a permanent covalent bond between polished and activated oxide surfaces.

**Package:** A plastic structure that holds an integrated circuit and provides connections to other devices.

**Process Node:** A standardized manufacturing process that defines the size of the electrical elements and how densely they can be packed together.

**QP:** Quilt Packaging: An HDI electrical interconnect system using horizontally interlaced “nodules” along die edges; initially developed by Indiana IC.

**Rad-Hard:** Radiation Hardened: Components and sensors designed to handle exceptionally high levels of radiation.

**RDL:** ReDistribution Layer: An extra metal layer on an IC that makes its I/O (input/output) pads available to other locations of the device.

**SoC:** System on Chip or System-on-a-Chip: an integrated circuit that combines several different functions on a single die.

**STCO:** System Technology Co-Optimization: fabricating various chip functions separately, using the best technology for each, before assembling into a single unit.

**Substrate:** The semiconductor material underlying the circuitry of an IC, usually silicon.

**TCB:** Thermal Compression Bonding: Heating and applying mechanical pressure to two adjoining surfaces, facilitating diffusion of metals and forming a metallurgical bond.

**Through Silicon Via (TSV):** A vertical electrical connection that pierces the substrate.

**UVM:** Universal Verification Methodology: A standardized methodology for verifying IC designs.

**VHDL:** VHSIC Hardware Description Language: A hardware description language for IC design entry, documentation, and verification.

**W2W:** Wafer-to-Wafer (also wafer-on-wafer) stacking: Bonding and integrating whole processed wafers atop one another before dicing the stack.

**Wafer:** A disk of semiconductor material (usually silicon) on which integrated circuits can be fabricated.

**Wafer on Wafer:** See W2W.

**WoW:** Wafer-on-Wafer; see W2W.